In order to efficiently process high-bandwidth or high-dynamic range signals, designers often employ serial or parallel processing methods. Parallel processing is a technique in which a signal, or some portion of a signal, is introduced into two or more signal paths and processed simultaneously by the plural signal paths. Parallel processing allows the use of many subcircuits, each with potentially relaxed specifications, to perform the signal processing work of a single circuit with possibly more stringent specifications. Parallel signal processing provides many benefits, but it also raises some unique challenges. The parallel paths must have tightly controlled characteristics to provide the coordination necessary for efficient operation. A recombination operation usually follows parallel processing, and the accuracy and purity of the final result depends on having known and controlled characteristics in each of the parallel signal paths. Serial signal processing is a method utilizing a cascade of processing stages. A signal propagates from the output of one stage to the input of the next, and is usually modified in some way at each stage. Serial processing provides many of the benefits of parallel processing through the relaxation of requirements at each stage to meet a given overall performance goal. The challenges of maintaining well-controlled characteristics that apply to parallel signal processing are also relevant in serial signal processing. In order to efficiently process signals, the stages must have known and consistent behavior.
Parallel signal processing is a technique well-suited to implementation in an integrated circuit. Advantages of higher levels of integration include the ability to construct many circuits in a small physical space. Digital circuits have benefited greatly from technology advancements that enable higher levels of integration. Unfortunately, the performance of analog integrated circuits has generally not kept pace with the improvements seen by digital circuits. One way to improve analog circuit performance, while taking advantage of higher levels of circuit integration, is to utilize parallel processing techniques. By employing multiple circuits, properly coordinated, with outputs suitably combined, significant performance improvement is possible. FIG. 1A is a system block diagram of a parallel signal processing system 10 in accordance with the prior art. A signal 12 to be processed in a parallel system first passes from the input 14 through a splitting operation 16. The splitting operation may separate the signal into its constituent components such as amplitude, frequency, offset voltage, or phase. Or, in the simplest case, the entire signal may be distributed unmodified to the n outputs 18(1), 18(2), 18(3), . . . , 18(n) of the splitter. The signal, or a selected component of that signal, is then coupled into the n processing branches 20(1), 20(2), 20(3), . . . , 20(n) that make up the paths of the parallel processor 10. The processing branches may act independently of each other, or there may be some interaction among processing stages in different paths as illustrated by cross links 22(1), 22(2), 22(3), . . . , 22(n). One example of this interaction is an averaging function. The outputs of the signal paths are generally recombined as in recombiner block 24, in some cases as an analog process and in some cases as a digital process, according to the design and function of the processor. The accuracy of the final result 26 and the efficiency of the overall processing operation are heavily dependent on each signal path having an accurate implementation of the proper transfer function as required by the design of the processor 10.
Serial signal processing is an established and well-known technique for modifying the parameters of a signal by passing it through a series of processing stages. FIG. 1B is a system block diagram of a serial signal processing system 28 in accordance with the prior art. The signal parameter of interest could be signal power, as is the case with a signal propagating through many stages of amplification in a transmitter chain prior to coupling to an antenna Alternatively the signal parameter of interest could be the frequency of a signal as it is modified by the stages of a superheterodyne receiver. Many other parameters may be processed. Regardless of the specific parameter, serial processing is an important and generally necessary technique for processing signals that experience a wide parameter variation while processed by a system. By dividing the signal processing operation into a set of steps, it is possible to design a system that is robust and efficient in both design and implementation.
FIG. 1B illustrates some of the key attributes of serial signal processing. A signal 30, introduced into an input 32 of the system, is modified by the first processing stage 34. That stage 34 has an output 36 for coupling the modified signal into the input 38 of the next stage 40, where the signal undergoes further modification, possibly of a different nature. The signal propagates through as many stages as required (e.g., stages 42, 44 and 46), and experiences as many modifications as required, to extract the desired result from the cascade of stages (34, 40, 42, 44, 46) comprising the serial signal processing system 28. Signal propagation generally proceeds from the input 32 toward the output 48, through the processing stages (34, 40, 42, 44, 46). Versions of the input signal 30, modified by the processing stages, may be used by other stages further along the serial path, bypassing some stages in the process. All of the paths which are designed to propagate signals in the direction from the input 32 toward the output 48 of the serial signal processor 28 are considered “feedforward” paths (e.g., paths 50, 52). By contrast, “feedback” paths (e.g., paths 54, 56) convey signals from a stage or stages toward stages that are closer to the signal input 32 in the main propagation path. With proper design, serial processing systems can efficiently process signals of a widely varying nature, as are common in communication applications.
While providing many benefits, serial signal processing has some disadvantages. Errors in the processing of a signal in a serial system are cumulative. If a signal is corrupted in a stage of the system, the corrupted version of the signal propagates through subsequent stages of the system. This signal corruption may lead to increased power draw, reduced gain, further corruption due to mixing effects, or undesired system performance. Serial processing systems that employ feedback paths must have controlled and predictable characteristics of the feedback signals in order to ensure system stability. It is imperative, then, for each stage in a serial signal processing system to have well-controlled characteristics.
Many applications call for a combination of parallel and serial processing methods. Each of the signal paths in a parallel processor may include a cascade of stages in series, or a serial processing system may incorporate one or more stages utilizing parallel processing techniques. The design of a system with any combination of serial and parallel processing must consider all of the attributes of each method. The requirement for well-controlled signal response is especially relevant in systems employing a combination of parallel and serial methods.
In conventional integrated circuit design, engineers construct circuits from transistors, resistors, capacitors, and other standard circuit elements. These circuit elements have variances in their respective circuit parameters. For example, transistors have variances in their threshold voltage, width, and length. These variances are due in part to process and temperature gradients. Minimizing the error in parallel and serial circuits requires reducing the effects of these variances. Many techniques for reducing these effects are known in the art, including using large transistors, using lasers to trim resistors, using capacitors to dynamically match devices in response to on-chip error signals, and the like. In general, these approaches have significant disadvantages. For example, large transistors require large currents to operate at high speeds, consume relatively large amounts of die area and power, and do not compensate for temperature- or aging-induced errors. Likewise, using lasers to trim resistors necessitates large resistors, a time-consuming laboratory laser trim process, and again does not compensate temperature- or aging-induced errors. Using capacitors to dynamically trim circuit elements requires wideband error-feedback loops and relatively frequent updates due to the fact that most on-chip capacitors leak due to the thermal generation of carriers in pn junctions.
Consequently, there is a compelling need for a simple and compact means to trim circuit elements on chip, at a slow and deliberate rate, without rapid leakage or the need for frequent calibration updates.